Backqround of the Invention and Prior Art
This invention relates generally to phase locked loops and particularly to a variable speed phase locked loop that includes a variable gain phase detector for optimizing the pull-in range and noise immunity of the phase locked loop (PLL).
PLL's and phase detectors are well known in the art. The output of the phase detector is used to control the oscillator to reduce the error between the input signal and the reference signal and produce a locked condition. It is desirable for optimum signal pull-in performance to maximize the phase detector gain for controlling the oscillator when the input and reference signals are relatively far apart, i.e. when a maximum phase error is present. On the other hand, for stability, it is desirable to minimize the phase detector gain when the two signals exhibit a minimum absolute phase and the PLL is in the locked condition. Prior art attempts to achieve this desirable operating characteristic have been compromises in which the PLL has one gain when in a locked condition and a higher gain when in an unlocked condition.